In the field of power semiconductor devices and power semiconductor IC (Integrated Circuit) devices such as BCD devices (BCD: Bipolar-CMOS-DMOS), IGBTs and the like, one or more metallization layers are used to conduct large currents (high power currents).
The present assignee identifies its power semiconductor technologies as SPT (Smart Power Technology) and identifies the corresponding technological development stages or generations thereof with a number, i.e. SPT5, SPT6, SPT7.
For example, technology stage SPT6 uses power copper metallizations with a thickness of 20 μm as described, e.g., in DE 103 60 513 A1, which also describes an example of a power DMOS.
FIG. 4, which corresponds to FIG. 1 of DE 103 60 513 A1, shows a cross sectional view of a power DMOS comprising a substrate 1 (made e.g. of Si), field oxide layers 2, transistor and wiring/conductor structures 3, 4, 5, partly connected via plugs/vias 6,7, embedded in a plasma oxide layer 8. A power metallization 10′ of copper is deposited as the top layer of the multi-layer wiring/metallization structure.
In manufacturing such a power metallization made of copper (Cu), as described e.g. in US 2005/0127534 A1, the contents of which are incorporated herein by reference, a coating may be applied over the copper, for example by electrogalvanic plating or by electrochemical plating. An example of such a coating is a NiP/Pd/Au layer. The hard NiP layer has several functions, namely the prevention of interdiffusion of Pd, Au and Cu and to prevent that the needles of needle cards (probe) used when testing the final products, penetrate into the Cu. Furthermore, it is prevented that structures below the Cu layer, which are usually mechanically fragile, are damaged or destroyed during the testing or during the bonding. Bonding On Active (BOA) means bonding on bonding pads, which are positioned above electrically active structures as viewed in the pressure applying direction during bonding. BOA is possible if such a hard NiP layer has been applied, because the NiP layer prevents the force applied to the bonding pad during bonding from being transferred to the mechanically fragile structures.
BOA is preferable, because the chip area can be reduced by about 10%, if BOA is used.
However, NiP recrystallizes during thermal treatments such as forming gas tempering or soldering processes. Due to the recrystallization, the NiP layer shrinks to such an extent that cracks are generated in the layer. Usually, the cracks are generated in large structures and start in corners of the metallization layer structure.
Such cracks should be avoided in order to prevent moisture from reaching the copper.
A further problem generated by the shrinking NiP is caused by the high elasticity module of NiP, because the shrinking distorts the wafer disks such that they can not be processed anymore.
For these and other reasons, there is a need for the present invention.